Hi, in my schematic entry I use the altpll block to divide my clock. I`ve routet the outputs to GPIO pins and could measure them via oscilloscope. But when I use them for simulation in the waveform editor, there is just a low signal at the outputs. So, check out my screenshot, to see that the allclear button works, and the pll is going to start, after alclr is low. So it seems, that the pll works, and as I told you, I can measure the clock signals via oscilloscope at the gpio pins. So, what did I wrong? I would be happy, if someone could help me. best regards sektor

The PLL needs time to lock to the input clock. Try running your simulation longer (10ms ?) Try adding the 'locked' output of the PLL as a diagnostic aid.

Thank you, that might be the solution, I didn`t think about tht the pll isn`t locked yet. So thank you. But in the waveform simulation tool, i only can set the maximum simulation time to 100us. Is there a workaround, to capture the pll signals into the waveform editor?

Try using Modelsim. It doesn't have any such limitation.

Thank you for your answer. Yes, I tried. But I´m not experienced in ModelSim. so I tried the example from the User Guide. This works pretty. But I cannot implement my current project into ModelSim, because there are to many different signals and files, so I didn`t get it to work. Therefore I used the Waveform Editor. I`m sure, it is not so difficult, to simulate it via ModelSim, but I need a short introduction. So perhaps someone could assist me to getting started? When I open the directory "work" there are only the entities, but there are no I/O ports or something else to select and generate a waveform. In the msgs window, there is "No Data". Sorry about those silly questions, but I`m totally new in ModelSim, so how can we make this thing working? I also used Simulink to create some designs. It`s possible to start ModelSim out of Simulink, so the "wave"-window in ModelSim is automatically configured with the necessary signals. It is possible to have a solution like that out of quartus?? Hope to get some help, thanks a lot in advance. kind regards

If you look around, you will find some tutorials (like this one, which is older but still relevant: http://www.altera.com/literature/ug/ug_gs_msa_qii.pdf) But getting started is quite easy by letting Quartus do much of the work for you: 1) get your project completed to the point that Quartus is able to compile it. 2) if you haven't already, create a testbench HDL file. At a minimum, just have it generate a clock and reset for your system. 3) in Quartus, go to Assignments->Settings.... -> EDA Tool Settings -> Simulation and review the other settings, but go down to the NativeLink section and click on "Compile test bench" and then define your test bench (give it a name, tell it where your testbench HDL file is). This is shown on page 5 of the PDF mentioned above. 4) execute a Quartus compile. During this process, Quartus will write a Modelsim .do TCL script to command Modelsim how to compile your source and simulate it with your testbench. 5) after the compilation completes, click on Tools->Run Simulation Tool-> RTL Simulation.. Quartus will launch Modelsim and have it run the .do script that it just wrote for you. It will compile your HDL files, load your testbench top level into the simulator, add the testbench signals to the wave window, and start it executing. There's much more you can do beyond this, but hopefully this can get you started.

Quartus2 - altpll megawizard plugin - no clock output in simulation waveform editor

11 Replies

Altera_Forum
Honored Contributor
11 years ago
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Modelsim stopped the simulation with an error, because a file called "../../rtl_work.filename" could not be found.
The file isn`t in the directory, so how to create this file?

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I'm not sure what that file is or how you would create it. If you post your project, someone may take a look.

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And let me ask you, what exactly do you mean with "modify it to add clk/reset generation".
Is it to add a clock and a reset from the IP catalog?

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Open the counter.vt file and search for 'clk' and 'reset_n' and you will see where I added my clk/reset generation. You need to do the same/similar in your own test bench file.

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For your information, actually i receive the clock from an external signal, so i just got an input port. In the waveform editor, you could generate a clock. Is it possible to work like that in Modelsim to or is it necessary to use the IP blocks as mentioned in my question above?

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The tutorial PDF tells you how to do it in Modelsim. My project and my suggestion is to do it in (Verilog) HDL in your test bench file. It's pretty simple, and yes almost all projects get set up like this.

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Quartus2 - altpll megawizard plugin - no clock output in simulation waveform editor

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