Quartus VHDL compiler returns error 10818

Here is the VHDL code,i have make it OK!

It works!

library IEEE;

use IEEE.std_logic_1164.all;

entity addrdecoder is

port(

inbit : in std_logic;

clk : in std_logic;

sel : in std_logic;

dataout : out std_logic_vector(7 downto 0);

complete : out std_logic;

flat: in std_logic_vector(2 downto 0)

);

end addrdecoder;

architecture arc_addrdecoder of addrdecoder is

signal dataout_s : std_logic_vector(7 downto 0);

signal done: std_logic;

signal currbit : std_logic_vector(2 downto 0);

begin

process(sel,clk,done)

begin

if(sel='1') then

dataout<=x"0f";

dataout_s<=x"0f";

done<='0';

currbit<="000";

elsif(clk'event and clk='1' ) then

if done='0' then

case currbit is

when "000" =>

dataout_s(7)<=inbit;

currbit<="001";

when "001" =>

dataout_s(6)<=inbit;

currbit<="010";

when "010" =>

dataout_s(5)<=inbit;

currbit<="011";

when "011" =>

dataout_s(4)<=inbit;

currbit<="100";

when "100" =>

dataout_s(3)<=inbit;

currbit<="101";

when "101" =>

dataout_s(2)<=inbit;

currbit<="110";

when "110" =>

dataout_s(1)<=inbit;

currbit<="111";

when "111" =>

currbit<="111";

done<='1';

when others =>

dataout_s<=x"FF";

done<='0';

currbit<="000";

end case;

if(done'event and done='1') then

if(flat=dataout_s(6 downto 4)) then

dataout<=dataout_s;

dataout(0)<=inbit;

end if;

end if;

end if;

end if;

end process;

complete<=done;

end arc_addrdecoder;

configuration cfg_addrdecoder of addrdecoder is

for arc_addrdecoder

end for;

end cfg_addrdecoder;