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Altera_Forum
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18 years ago

Quartus VHDL compiler returns error 10818

Hello. I am trying to compile some VHDL code in Quartus II and the compiler returns me a bunch of errors: Warning (10631): VHDL Process Statement warning at AddrDecoder.vhd(20): inferring latch...
Altera_Forum's avatar
Altera_Forum
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18 years ago

One last thing; you'll need to rework the cycle timing if you intended to load 8 inbits in a row. Otherwise changing the final code from asynchronous to synchronous will make you load the last "inbit" value one cycle late. To fix, you could move the final code into the 'when "111"' clause itself. But I'd recommend that you look up shift registers instead and rewrite your code.