Quartus VHDL compiler returns error 10818

You have two problems in your code.

First, your reset is asynchronous, but it deviates from the standard idiom for registers with asynchronous resets. Many synthesis tools require that certain hardware constructs be described with very specific idiomatic code, because they aren't intelligent enough to infer the right thing in every situation. Registers with asynchronous resets are one of those constructs. I think you may find that you have to replace your "else if(clk'event ... ) then ... end if; end if;" with "elsif (clk'event ... ) then ... end if;" to make Quartus happy. You may also have to move the "and done = '0'" into a nested if statement of its own. I'm not sure how much of that will be necessary though; Quartus may be one of the more flexible tools in this regard.

Secondly, your "if(done'event and done='1') then" code is well and truly unsynthesizable. You've written it to say that the comparison should be done _immediately_ once done is loaded with '1' (i.e., without waiting for the next clock edge) and that the results should be loaded asynchronously. That's just not doable in hardware. You need to move it into your clocked code above and remove the done'event part.