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Altera_Forum
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12 years ago

Quartus synthesis'result and RTL function are mismatch

Hi,All I using one design using system verilog and compile this design on Quartus 12.1 And I got the gate level netlist which functionality are not the same with RTL. And then I do s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hi,

After I try the Q13.0 sp1, the mismatch in testCase.tar.gz didn't go away. I wonder if you still need test bench to figure out the problem. If yes, I will spent some time try to do tb bench when I have free time.