Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Quartus synthesis'result and RTL function are mismatch

Hi,All I using one design using system verilog and compile this design on Quartus 12.1 And I got the gate level netlist which functionality are not the same with RTL. And then I do s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hi,

I and my colleague find another RTL/synthesis's mismatch and we still use Q12.1 , but maybe you have interest to check it out.

Attaching file contain test bench(stim.sv) and test case(testCase.sv) we make.

Ya-Chau