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Altera_Forum
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12 years ago

Quartus synthesis'result and RTL function are mismatch

Hi,All I using one design using system verilog and compile this design on Quartus 12.1 And I got the gate level netlist which functionality are not the same with RTL. And then I do s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I compiled in Q13.0 and in the both cases see registers driving that output, so if you're using an older version, it appears to be fixed.