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Altera_Forum
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12 years ago

Quartus synthesis'result and RTL function are mismatch

Hi,All I using one design using system verilog and compile this design on Quartus 12.1 And I got the gate level netlist which functionality are not the same with RTL. And then I do s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

HI,

Because this .sv is come from part of my design,it will take some time if you still need testbech.

But if you check the the synthesis result in mismatch folder using "Technology Map viewr" and check the output pin " fifoOut_dat", you will found those pin was assign to zero.

If you check the the synthesis result in match folder using "Technology Map viewr" and check the output pin " fifoOut_dat", you will found those pin was assign to part of design.

Ya-Chau

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If there's a synthesis bug, I would file a Service Request. I would also be very clear in showing snapshots from gate-level simulation and RTL simulation and what is different, as well as testbenches to run the simulations. Right now it's just the .sv files, which nobody would know how to simulate, let alone where to look for mismatches.

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