Quartus' synthesis of a CPU's register file

Hi,

Im not using a read enable signal at all, the ALU is always reading the register file every clock cycle.

/*CPU register file*/
 
module registers
#(parameter DATA_WIDTH=16)
(
	input logic clk, we,
	input logic [(DATA_WIDTH-1):0] wdata,
	input logic [4:0] rdest,
	input logic [4:0] rs1,
	input logic [4:0] rs2,
	output logic [(DATA_WIDTH-1):0] rdata1,rdata2
);
 
	// Declare the RAM variable
	logic [DATA_WIDTH-1:0] gpr [0:24];
 
	//initialise memory to 0
	initial
		for(int i=0; i<25;i++)
			gpr[i] = '0;
	
	
	always@(posedge clk)
	begin
		// Write enable
		if (we)
			gpr[rdest] <= wdata; //synchronous write
	end
	
	
	//read process
	assign rdata1 = gpr[rs1];
	assign rdata2 = gpr[rs2];
	
 
endmodule

The output rdata1 and rdata2 are fed into further registers (ID/EX) as shown below as the processor is pipelined.

I didn't want the registers to be implemented as on-chip memory.

Although im more curious to know why Quartus did rather than prevent it.

Thanks for the tips!

However, I am still confused about a certain aspects of this.

The code I showed you above stayed the same and was implemented in two different processors.

One was a pipelined processor and in that the register file was synthesised into altsync_ram and used memory bits.

The other processor was non-pipelined and the register file was synthesised into registers/ALMs and used no memory bits.

Im confused about how the same code can get synthesised differently just by being implemented in different top level designs.

Thanks