Quartus synthesis constrain

Hi,

In my project, the following code was to delay the data, I want to use the logic elements to implement in fpga, but the Quartus automatically use altshift_taps to implement which will cost one M9K.

Does there any constrains to constrain it using logic elements?

Thanks,

FPGA: EP3C40

QUARTUS II 8.1

--

-- delay the input data

--

pes_ua_array(0) <= pes_ua;

pes_ua_fs_array(0) <= pes_fs_ua;

pes_ua_delay:

for i in 1 to 13 generate

process(rst,clk)

begin

if (rst = '1') then

pes_ua_array(i) <= (others=>'0');

pes_ua_fs_array(i) <= '0';

elsif (clk'event and clk = '1') then

if (pes_v_ua = '1') then

pes_ua_array(i) <= pes_ua_array(i-1);

pes_ua_fs_array(i) <= pes_ua_fs_array(i-1);

end if;

end if;

end process;

end generate;