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Altera_Forum
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10 years ago

Quartus Router Congestion

Hello all, I have a Cyclone V A9 device (300k LEs) and a big design that fit it 95% ALM 12% Memory bits 37% DSP. 14% of ALM are unavailable due to LAB input limits and wide-signals conflicts so...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Yes, a simple UART to talk to external world.

I tried with max fanout limit of 90 but now I am out of LAB..

I am revisiting reset logic to reduce congestion..

Wow.. a 952K LEs full.. I hope compile times is good enought :)