Quartus Router Congestion

sometimes you just have to do manual register duplication in the HDL - its not too hard, but a little tedious.

Find some regs (a PLL is obviously going to have a high fanout) with a high fan out and use the maxfan attribute on them in the hdl, so that synthesis automatically duplicates a register when the fanout gets too high. Or you can manually duplicate the register and use the preserve synthesis attribute to prevent the two being merged. Then have separate parts of the design fed from the two separate (but identical) registers.