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Altera_Forum
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10 years ago

Quartus Router Congestion

Hello all, I have a Cyclone V A9 device (300k LEs) and a big design that fit it 95% ALM 12% Memory bits 37% DSP. 14% of ALM are unavailable due to LAB input limits and wide-signals conflicts so...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hello tricky,

This is my Quartus report:

Maximum fan-out node pll:u_pll|pll_0002:pll_inst|altera_pll:altera_pll_i|outclk_wire[0]

Maximum fan-out 68382

Total fan-out 910053

Average fan-out 3.92

I have enabled register duplication, now is compiling with three design partitions with logiclock regions with auto size and location. With custom logiclock regions (following altera guidelines) design failed into routing.

Thanks