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Hello,
It also gives another error : Error (10192): Verilog HDL Defparam Statement error at
analysis.sv(17): value for parameter "bitw_ofcalc" must be constant expression. And solution lies in this.
To solve this you can use : localparam int bitw_ofcalc = test_pkg::test_calc(BITW);
It would give you your expected result.
Thanks,
Bhaumik
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Thanks for replying.
The line you suggest to change is just illustrating the using of another module. I want to determine the bitwidth of signal bus 'sigs' in interface through the interface instance, for the interface can be instantiated with various value on parameter 'BITW', and the module passed the instance as a port can only determine the signal's bitwidth by using system function '$size'. So I can't directly pass the parameter 'BITW' to function ‘test_pkg::test_calc'.
I had read the IEEE STD 1800-2012, and it seemed that there was no issue dissatisfy the constant function rule in chapter 13.4.3. I don't know whether there is some mistake or bug in the code above, could you help me check it?
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