--- Quote Start ---
Hello,
It also gives another error : Error (10192): Verilog HDL Defparam Statement error at
analysis.sv(17): value for parameter "bitw_ofcalc" must be constant expression. And solution lies in this.
To solve this you can use : localparam int bitw_ofcalc = test_pkg::test_calc(BITW);
It would give you your expected result.
Thanks,
Bhaumik
--- Quote End ---
Thanks for replying!
Well, In the example code the purpose of using '$size(tifi.sigs,1)' is to determine the vector's bitwidth automatically, for the interface 'test_if' has an instantiate-parameter named as 'BITW', it can be changed by user in coding. The next line of code is simulating the usage of instance in other code blocks or modules, the developer can not determine the bitwidth of that vector mannually without viewing the code of instance. I want synthesizer automatically determine the vector's bitwidth, in order to avoid some duplicated work of people, so the calling of '$size(tifi.sigs,1)' had better to be remained.
I prefered to recognize this error as a bug of synthesizer, but I'm not sure whether there is no fault or mistake in my code, could you check them for me? thanks very much!
Honored Contributor
