Quartus reporting unconstrained inputs and outputs on constrained paths

Hi Nurina,

The device I'm using is the 10AS066H2F34I1SG

I'm confused what you mean by the "LVDS BLOCK". What is that? Is that simply what pins are used when assigning to the IO_STANDARD LVDS?

I watched the video you linked and I am still confused. As I put I have reported the clocks and the offending clock clearly shows up as a defined clock in the "report clocks":
chs_clk_rx Base 6.666 150.0 MHz 0.000 3.333

But it is still showing as unconstrained. Are you saying that even clocks require input delays? That doesn't really make sense, since you have to refer the those delays to some kind of clock?

I am not sure I can provide a .QAR file through the forum due to proprietary concerns. I have set the following constraints in my SDC:
create_clock -name {chs_clk_rx} -period 150.000MHz [get_ports {chs_clk_rx}];
create_clock -name {lvds_rx_1} -period 150.000MHz [get_ports {s1_lvds_in[1]}];

The first signal does not show as constrained but the second does. They're both clocks but only the CHS_CLK_RX goes into a PLL. Could that cause any difference?