Quartus reporting unconstrained inputs and outputs on constrained paths

Hello Tyler,

When I run: report_ucp -panel_name "Unconstrained Paths"

I still see:

chs_clk_rx: No input delay, min/max delays, false-path exceptions, or max skew assignments found

I have definitely constrained this signal as a clock because when I run: "report_clocks" it is clearly listed:

chs_clk_rx Base 6.666 150.0 MHz 0.000 3.333

This report is saying that you have not set any I/O timing constraints. Yes you have created the clock but since this clock is at the I/O pin, Timing Analyzer expects I/O constraints such as set_input_delay, set_min_delay, set_max_delay, etc.

You may find this video training useful: https://www.youtube.com/watch?v=ggWxledaBFg&t=1085

I'm not sure why I'm seeing this issue. I have other clocks constrained identically, for example:

set_location_assignment PIN_B5 -to s1_lvds_in[0] ; # BANK 3E : 1.8V hpc_ha09_p

set_instance_assignment -name IO_STANDARD LVDS -to "s1_lvds_out[0]"

set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to "s1_lvds_in[0]" -entity achilles_top

Have you added I/O constraint to this path? If not, can you share your .qar file so I can investigate further? To generate this, go to Project>Archive Project.

I'm also still seeing on the report unconstrained signals that my (n) output pins are all still showing up as unconstrained.

Is there a restriction to using the IO_STANDARD LVDS when you are NOT using the Intel LVDS IP CORE to drive the signals?

You can ignore the unconstrained paths reported at (n) pins, so that Timing Analyzer won't run two separate path. As long as you are using the LVDS block in the FPGA, you can use IO_STANDARD LVDS.

Regards,

Nurina