Quartus reporting unconstrained inputs and outputs on constrained paths

Hi Nurina thanks for your response.

So I removed those constraints from the pin.tcl file and deleted them in .qsf so that it would be properly re-assigned.

When I run: report_ucp -panel_name "Unconstrained Paths"

I still see:
chs_clk_rx: No input delay, min/max delays, false-path exceptions, or max skew assignments found

I have definitely constrained this signal as a clock because when I run: "report_clocks" it is clearly listed:
chs_clk_rx Base 6.666 150.0 MHz 0.000 3.333

The tcl setting for this pin is:
set_location_assignment PIN_K6 -to chs_clk_rx ; # BANK 3D : 1.8V lpc_la28_p
set_instance_assignment -name IO_STANDARD LVDS -to "chs_clk_rx"
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to "chs_clk_rx" -entity achilles_top

I'm not sure why I'm seeing this issue. I have other clocks constrained identically, for example:

set_location_assignment PIN_B5 -to s1_lvds_in[0] ; # BANK 3E : 1.8V hpc_ha09_p
set_instance_assignment -name IO_STANDARD LVDS -to "s1_lvds_out[0]"
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to "s1_lvds_in[0]" -entity achilles_top

The only difference is that "chs_clk_rx" is coming into a global clock pin and going into a PLL whereas the other signals are not.

I'm also still seeing on the report unconstrained signals that my (n) output pins are all still showing up as unconstrained.

Is there a restriction to using the IO_STANDARD LVDS when you are NOT using the Intel LVDS IP CORE to drive the signals?

Thanks,

Tyler