Quartus reporting unconstrained inputs and outputs on constrained paths

Hi Nurina,

Thanks for getting back to me! I was off for a few days.

To clarify a bit I am not using the Intel LVDS IP core to drive the signals, but rather our own logic. However in the pin planner I have set the signals to LVDS I/O standard as shown:

The commands I use are:

set_location_assignment PIN_L6 -to chs_clk_rx(n) ; # BANK 3D : 1.8V lpc_la28_n
set_location_assignment PIN_K6 -to chs_clk_rx ; # BANK 3D : 1.8V lpc_la28_p

set_instance_assignment -name IO_STANDARD LVDS -to "chs_clk_rx(n)"
set_instance_assignment -name IO_STANDARD LVDS -to "chs_clk_rx"

set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to "chs_clk_rx(n)" -entity achilles_top
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to "chs_clk_rx" -entity achilles_top

Which are identical to other LVDS pins I'm using.

My output signals are similar:

set_location_assignment PIN_A6 -to s1_lvds_out[0](n) ; # BANK 3E : 1.8V hpc_ha05_n
set_location_assignment PIN_B6 -to s1_lvds_out[0] ; # BANK 3E : 1.8V hpc_ha05_p

set_instance_assignment -name IO_STANDARD LVDS -to "s1_lvds_out[0](n)"
set_instance_assignment -name IO_STANDARD LVDS -to "s1_lvds_out[0]"

Is there a constraint I'm missing by not using the Intel LVDS IP core?

Thanks,

Tyler