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AWilc1's avatar
AWilc1
Icon for New Contributor rankNew Contributor
7 years ago

Quartus reducing design undesirably

I have a problem in which I am trying to design a butterfly PUF (butterfly latch circuit) using d-types. When I try to synthesise this circuit quartus will show that it is using 0 logic cells from m...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
7 years ago

You can also go to the Verilog file -> right click -> insert template -> find the attribute for the 1 you want. This will list down all the available attribute where Quartus offers.

Thanks​