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AWilc1's avatar
AWilc1
Icon for New Contributor rankNew Contributor
7 years ago

Quartus reducing design undesirably

I have a problem in which I am trying to design a butterfly PUF (butterfly latch circuit) using d-types. When I try to synthesise this circuit quartus will show that it is using 0 logic cells from m...
AndyN's avatar
AndyN
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Does your design actually drive anything? If it's a purely internal piece of logic then, yeah, Quartus will optimize it out with standard settings.

The simplest way to stop it optimizing it out is to add a noprune constraint to the output signal. Note that if it's optimizing it out in a "real" design rather than a test one, it has a reason for removing it that you'll need to investigate.

Hope that helps,

Andy