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xxerexxaa
New Contributor
New ContributorQuartus Prime20.1 can't compile systemverilog syntax
我在使用modsim编译成功并且成功仿真以后想使用quartus烧录至FPGA上发现许多类似于class 和数学函数的使用在quartus里无法编译。 我已经修改了quartus prime 20.1 的编译器为SystemVerilog但是还是无法编译class。请问有人遇到类似的情况吗？ 据我所知可能是软件本身的问题，但是我的导师希望我最好还是使用quartus，所以请问有什么比较好的不...
ShengN_altera
Super Contributor
Super ContributorHi,
Check this link https://www.doulos.com/knowhow/systemverilog/systemverilog-tutorials/systemverilog-classes-tutorial/ and this link https://verificationguide.com/systemverilog/systemverilog-class/, SystemVerilog introduces classes as the foundation of the testbench automation language. That's why classes can be used in simulator but not in compiler tool like Quartus.
Thanks,
Best Regards,
Sheng
