Quartus Prime pro reported error during full Compilation

hi, Richard,

I found this error is related to the pin assignment of the Lane 3 of bank 2K, which i have discussed via E-mail with you.

when I disable the EMIF, the pins can be driven normally. when I enable the EMIF, the pins can not be driven by logic.

and i also found an Article with ID 000079165 from intel website, it mentioned that if HPS EMIF is enabled, Lane 3 of bank 2K can only be used as FPGA input only. I think this is the root cause.

if I delete the drive logic of these pins from my design, this IE will disappear.

But the article also mentioned that the Quartus Prime software version 15.1.1 and earlier do not check for these restrictions, and the patch for above restriction is also scheduled to be added to a future version of the Quartus Prime software.

But Quartus pro 22.4, what i am using, this version only report this IE which triggerd by this pin assignment restriction and doesn't report error as you showed to me.