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ELIT1's avatar
ELIT1
Icon for New Contributor rankNew Contributor
1 year ago

Quartus Prime Pro 24.1 RAM Inference problems

When trying to infer Block-RAM from the attached System Verilog code the following problems occurred: 1 - when used 'rd_outcken' input (RDOUTCKEN_USED = "YES") - out registers not packed to memory ...
Hdl
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

Thanks you for your feedback,

Just take note: the IP editor that you created, will generated some file. This file you can use it as verilog file if you wish to do that. But general advise is to use the .ip file as it is more clean and easier to debug for your whole design. We shall close the thread, thanks again.