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ELIT1's avatar
ELIT1
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1 year ago

Quartus Prime Pro 24.1 RAM Inference problems

When trying to infer Block-RAM from the attached System Verilog code the following problems occurred: 1 - when used 'rd_outcken' input (RDOUTCKEN_USED = "YES") - out registers not packed to memory ...
Hdl
ELIT1's avatar
ELIT1
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1 year ago

Hi.

Altera memory blocks have 4 clock enable inputs:
clocken0, clocken1, clocken2, clocken3
and 6 parameters:
clock_enable_input_a, clock_enable_output_a,
clock_enable_input_b, clock_enable_output_b,
clock_enable_core_a, clock_enable_core_b.

By setting these parameters: "BYPASS" / "NORMAL" / “ALTERNATE” / “USE_INPUT_CLKEN” -

determines the connection and use of clock enable inputs.

Please see the attached file created by Quartus Prime Pro 24.1 IP PARAMETERS EDITOR.

I want to have a synthesizable RTL equivalent.

Thanks,

ELIT1