Quartus Prime Lite keep hierarchy

Thanks for the reply,

however that is not what I want. I mean I am currently using that statement, which helped in preventing weird optimizations that lead to timing errors (I really do not understand how a compiler optimization could lead to hold time problems, especially with aggressive performance settings while removing registers and free resources available). But in the end it does not help really archive what I want to do. I can not use the statement on all registers as in the end it would archive the same as completely disabling it via the global option and thus not fitting on the FPGA any more.

With Xilinx I can use the keep_hierarchy statement and it fits on similar sized Artix‐7 without any problems. No timing issues or anything. So is there any possibility that I can do the same on the Cyclone V E or am I basically out of luck as long as I do not foot the 3000$ bill?

Best regards
Christian

Thanks for the reply.

Well it is not exactly what I want. I am currently using that and it helped with the timing problems. But it cuts down on the optimisation and thus really increases the required resources.

With Vivado you have the KEEP_HIERARCHY attribute which basically does exactly what I want to do.

As you may have seen in my other questions I am implementing a neural network via shiftw in the FPGA. I have the network structured by layers with each layer having their own controls.

If I do not use any attributes Quartus merges all the controls and thus creates very long signal path, it literally goes over the entire FPGA. If I use Vivado with keep_hierarchy it groups the individual layers with the controls on the FPGA and thus archives a lot better timing while not increasing resource use dramatically as it can still optimize quite a bit inside the layers.

Just disabling the merging and optimizations of the controls entirely is not an easy option. There are quite a lot of duplicates and I thought Quartus would do a better job than I can do myself. If I currently disable the optimization for the controls it just blows up my design by a factor of about 2 making it way to big for the FPGAs I have at hand.

I did somewhat combat it with the keep attribute but it still is a lot worse in both timing and resources than just the simple attribute with Vivado.

So is there any way I can archive something like that without having to try to optimize the controls by hand and then using the keep attribute?

Best regards
Christian