Forum Discussion
New ContributorQuartus Prime Lite keep hierarchy
Without resorting to design partitioning using Standard, the only thing I can think of is using Logic Lock physical partitioning in the Chip Planner. I forget if it's available in Lite, though, but I think it is (EDIT: nope, Standard and Pro only).
I think you have to bite the bullet.
Super ContributorWoznik,
Intel do have synthesis attribute like noprune to prevent Quartus from optimizing away register. You may find them more via in Quartus --> New file --> select Verilog/VHDL file --> insert template --> synthesis attribute.
Christian_WoznikThanks for the reply,
however that is not what I want. I mean I am currently using that statement, which helped in preventing weird optimizations that lead to timing errors (I really do not understand how a compiler optimization could lead to hold time problems, especially with aggressive performance settings while removing registers and free resources available). But in the end it does not help really archive what I want to do. I can not use the statement on all registers as in the end it would archive the same as completely disabling it via the global option and thus not fitting on the FPGA any more.
With Xilinx I can use the keep_hierarchy statement and it fits on similar sized Artix‐7 without any problems. No timing issues or anything. So is there any possibility that I can do the same on the Cyclone V E or am I basically out of luck as long as I do not foot the 3000$ bill?
Best regards
Christian- sstrell
It sounds like you want to use the "keep" and "preserve" synthesis attributes instead of noprune.
You don't need incremental compilation to use synthesis attributes. Incremental compilation just tells the compiler to not touch a part of your design that's already compiled (locked down essentially). It has nothing to do with optimizing away logic.
