Forum Discussion
New ContributorQuartus Prime Lite keep hierarchy
Without resorting to design partitioning using Standard, the only thing I can think of is using Logic Lock physical partitioning in the Chip Planner. I forget if it's available in Lite, though, but I think it is (EDIT: nope, Standard and Pro only).
I think you have to bite the bullet.
New ContributorThanks for the reply.
Well it is not exactly what I want. I am currently using that and it helped with the timing problems. But it cuts down on the optimisation and thus really increases the required resources.
With Vivado you have the KEEP_HIERARCHY attribute which basically does exactly what I want to do.
As you may have seen in my other questions I am implementing a neural network via shiftw in the FPGA. I have the network structured by layers with each layer having their own controls.
If I do not use any attributes Quartus merges all the controls and thus creates very long signal path, it literally goes over the entire FPGA. If I use Vivado with keep_hierarchy it groups the individual layers with the controls on the FPGA and thus archives a lot better timing while not increasing resource use dramatically as it can still optimize quite a bit inside the layers.
Just disabling the merging and optimizations of the controls entirely is not an easy option. There are quite a lot of duplicates and I thought Quartus would do a better job than I can do myself. If I currently disable the optimization for the controls it just blows up my design by a factor of about 2 making it way to big for the FPGAs I have at hand.
I did somewhat combat it with the keep attribute but it still is a lot worse in both timing and resources than just the simple attribute with Vivado.
So is there any way I can archive something like that without having to try to optimize the controls by hand and then using the keep attribute?
Best regards
Christian
Super ContributorWithout resorting to design partitioning using Standard, the only thing I can think of is using Logic Lock physical partitioning in the Chip Planner. I forget if it's available in Lite, though, but I think it is (EDIT: nope, Standard and Pro only).
I think you have to bite the bullet.
- Christian_Woznik
Ok thank you for your answer. I guess I will just drop the Intel FPGA then and just continue with the Xilinx one. A shame that such a feature is locked behind such a paywall with Intel.
I really do not understand why you would do it if you want to sell chips especially if the competition does not do that.- sstrell
Cyclone V is a low-end device family at this point. The Lite version of Quartus lets anybody using the low-end devices get into creating basic designs without having to pay for design software (aka hobbyists and non-production designs). Anything more complicated requires more advanced features available in Standard and Pro.
- Christian_Woznik
Well so is the Artix-7 family for Xilinx. I really do not see big selling point for the Cyclone if I compare those two. And Xilinx will also have the new Artix US+ in the free version, so you can get PCIe Gen4 & DDR4 without having to pay for the software licence (once it finally arrives in 2022).
I can understand why you would want to limit certain class of FPGA to the paid version, if you need that kind of system you can pay it, but I do not understand why you have to limit functions even with the series where you offer a free version. I mean the cyclone V also goes up to 300k LE so not really a very small device in the end.
For myself I am just glad that I have bought both boards now for myself.
