Quartus Prime (Lite Edition): timing violation signals on Netlist

Use the Timing Analyzer (aka TimeQuest). From the Quartus Compilation report in the Timing Analyzer folder, right-click the clock domain(s) in the summary reports that are failing timing and select Report Timing. This will create a detailed timing report in the timing analyzer. You can then right-click a failing timing path and cross-probe to the Chip Planner or the Technology Map Viewer to get more detail about the failing path(s).