Forum Discussion
Hi @pharez
I wanted to suggest trying out the "counter" design template available in Quartus.
You can simply right-click on a blank Verilog/VHDL file and select the counter template. This can help eliminate any potential design or schematic issues causing the problem. In any text editor, right-click->Insert Template -> Verilog HDL -> Full Designs -> Arithmetic -> Counters.
Additionally, I recommend not spending too much time learning waveform simulation. As your design becomes more complex, it's recommended to use the Questa Intel FPGA Edition simulation tool.
It can handle more intricate designs and provide better insights.
Link: [https://www.intel.com/content/www/us/en/docs/programmable/703090/21-1/simulation-quick-start.html]
Hope these tips help! Let me know if you have any further questions or need additional assistance.
Best Regards,
Richard Tan