New ContributorQuartus Prime Light Waveform Simulation Error
Hello, I am having trouble with running timing and functional simulations in the Simulation Waveform Editor.
I have been following a a tutorial described in the book "Circuit Design With VHDL" by Volney A. Pedroni. The tutorial detailes the step-by-step instructions for creating ans simulation a registered adder in VHDL. I have Succsessfully compiled the code and viewed the Netlist in RTL and TM viewer, but I am getting an error when I try to simulations in the Simulation Waveform Editor.
This is the error message i get:
# ** Error: Waveform.vwf.vht(127): near "~": syntax error
# ** Error: Waveform.vwf.vht(134): near "~": syntax error
# ** Error: Waveform.vwf.vht(141): near "~": syntax error
# ** Note: Waveform.vwf.vht(144): VHDL Compiler exiting
# End time: 22:24:20 on Aug 18,2022, Elapsed time: 0:00:00
# Errors: 3, Warnings: 0
# ** Error: C:/intelFPGA_lite/20.1/modelsim_ase/win32aloem/vcom failed.
# Executing ONERROR command at macro ./registered_adder.do line 4
Error.
This is what the editor looks like. I have not changed any of the default Simulation settings:
This is my the full VHDL code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity registered_adder is
port (
clk: in std_logic;
a, b: in std_logic_vector(2 downto 0);
sum, sum_reg: out std_logic_vector(3 downto 0));
end entity;
architecture rtl of registered_adder is
begin
sum <= std_logic_vector( ('0' & unsigned(a)) + unsigned(b) );
process(clk)
begin
if rising_edge(clk) then
sum_reg <= sum;
end if;
end process;
end architecture;
This is the RTL Viewer:
I am very new to this, so I would appreciate as much help as I can get
