New Contributor
Super Contributor~ALTERA_NCEO~
~ALTERA_DATA0~
~ALTERA_ASDO~
~ALTERA_NCSO~
~ALTERA_DCLK~
These are reserved dedicated programming pins. You can't and not necessary to simulate them. Not need to include those pins in Simulation Waveform Editor.
Best Regards,
Sheng
p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.
New ContributorI am having this error when I try to simulate a design:
# vsim -c -t 1ps -L cyclonev -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.dec2to4_vhd_vec_tst
# Start time: 14:32:00 on Aug 23,2022
# ** Note: (vsim-3812) Design is being optimized...
# ** Fatal: Unexpected signal: 11.
# ** Note: Vopt Compiler exiting
# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=1, Warnings=0.
# Error loading design
Error loading design
# End time: 14:32:01 on Aug 23,2022, Elapsed time: 0:00:01
# Errors: 1, Warnings: 0
Error.
The code is very simple one which is given below:
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY dec2to4 IS
PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
En : IN STD_LOGIC ;
y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ;
END dec2to4 ;
ARCHITECTURE Behavior OF dec2to4 IS
SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ;
BEGIN
Enw <= En & w ; -- Notice how to combine two signals into one
WITH Enw SELECT
y <= "1000" WHEN "100",
"0100" WHEN "101",
"0010" WHEN "110",
"0001" WHEN "111",
"0000" WHEN OTHERS ;
END Behavior ;
