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EPeet's avatar
EPeet
Icon for New Contributor rankNew Contributor
7 years ago

Quartus Prime: Inferring latch(es) for clocked process

I have a normal process with async reset and clock like below: request_pulse : in std_logic; signal pulse_in_d : std_logic; signal request_int : std_logic; signal flop_d : std_log...
Tricky's avatar
Tricky
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

As this is a code snippet, and doesnt reflect the real code, we can only guess as to what the problem is.

But in your conditions, Pulse_in_D is only assigned a value during reset, and cannot be assigned any values when reset = '1', hence you've made a latch with reset='0' as the enable.