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EPeet's avatar
EPeet
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7 years ago

Quartus Prime: Inferring latch(es) for clocked process

I have a normal process with async reset and clock like below: request_pulse : in std_logic; signal pulse_in_d : std_logic; signal request_int : std_logic; signal flop_d : std_log...
EPeet's avatar
EPeet
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7 years ago

Interesting.

When I simply replaced the generics (set either to true or false) by input ports (tied either to '1' or '0'), the warnings about the latches are gone.

Seems to me like a tool bug...