Quartus Prime and avalon mm bridge bit width meaning

I apologize for the confusion. It appears that your follow-up question is specifically related to the HPS, which falls outside my area of expertise.

In order to receive accurate and helpful assistance, I recommend creating a new thread in the FPGA Embedded section of the forum. https://community.intel.com/t5/Intel-SoC-FPGA-Embedded/bd-p/soc-fpga-embedded-development-suite

I understand this may cause some inconvenience, and I genuinely apologize for that.

However, by starting a new discussion in the appropriate section, you'll have a better chance of receiving the assistance you need from experts in the field.

Thank you for your understanding.

Best Regards,

Richard Tan