Quartus Prime and avalon mm bridge bit width meaning

Hi,

I now have a question.

If in FPGA side I have a avalon mm slave IP with 4 32-bit registers, the bridge is linked to the h2f Axi bridge,

so the first reg is addressed as IP_bridge_addr (0xC000_0000 + ip offset)

And in HPS I address the IP like:

uint32_t* reg_ip = (uint32_t*) IP_bridge_addr.

with reg_ip + 1, it is pointed to the next reg or just forward 8 bits?

And how to write an IP with constant regs of each 32 bits wide, like all the Altera IPs and call it in HPS with pointer + x (x means the xth reg) .

Is that related to the ava bridge width and AXI bridge width?

Thank you

Reguards.