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CAlex
Contributor
ContributorQuartus Prime and avalon mm bridge bit width meaning
Hi, Im so confused about each settings on width settings in quartus prime. 1. If Im not wrong, every address in QP is byte. So 0x1 = 8bit instead of 1bit? Why? 2. In HPS, what is the meaning of t...
RichardT_altera
Super Contributor
Super ContributorDropping a note to ask if my last reply was helpful to you?
Do you need any further assistance from my side?
Best Regards,
Richard Tan
CAlexContributor
ContributorHi,
I now have a question.
If in FPGA side I have a avalon mm slave IP with 4 32-bit registers, the bridge is linked to the h2f Axi bridge,
so the first reg is addressed as IP_bridge_addr (0xC000_0000 + ip offset)
And in HPS I address the IP like:
uint32_t* reg_ip = (uint32_t*) IP_bridge_addr.
with reg_ip + 1, it is pointed to the next reg or just forward 8 bits?
And how to write an IP with constant regs of each 32 bits wide, like all the Altera IPs and call it in HPS with pointer + x (x means the xth reg) .
Is that related to the ava bridge width and AXI bridge width?
Thank you
Reguards.
