Forum Discussion
Altera_Forum
Honored Contributor
8 years agoHi VJR
1/ "However, those settings were still getting applied to my project" => make sure to check clear output directories checkbox in order to regenerate you IP files with the new options. 2/ I've tried to reproduce your issue. So I've generated an example design of Arria10 EMIF using quartus 16 pro and an I've added two additional clocks. The run was successful till assembling phase (which in contradiction with what you said). could you give more details about your issue and the error returned by the assembler. thanks kais