Occasional Contributor
Occasional ContributorWow, it's a carbon-copy from my post on 2/21. Is that <Alt><F3> or <Alt><F5>? (or more likely one followed by the other?)
Two days "idling", then scraped off your shoe. Nice. Nothing says "please go away" like being transitioned to community support.
The demo design included with the PCIe Avalon-MM core produces a Platform Designer entry that has a "generic component" instead of the PCIe core proper. This Generic Component appears to have all of the 2000-ish P-Tile parameters unrolled as a flat file (further evidence that Intel/Altera knows the PCIe Avalon-MM core generator is broken.) While no doubt comprehensive, this is not particularly useful unless you have the P-Tile API document that describes all of the various parameters and their inter-relationships. Any chance Intel/Altera can publish the API so we, the community, can move forward? The P-Tile hardware supports the Avalon-MM interface. The script generating the parameters is broken. Intel/Altera doesn't want to support it. Give me the ability to fix it myself.
Regular ContributorHi,
I understand your concern, I will remain this as open until you got a satisfies answer.
Please allow me to continue support you on your request, if you feel anything that I can help you to move on, please do not hesitate to let me know.
If you need P-tile API flow and list, you can get it at link below.
Regards,
Wincent_Intel
Occasional ContributorThose APIs are for software development/support of the interface. We, the community, would need access to the hardware APIs that define configurations and interconnects across the AIB/EMIB boundary. We have a copy of the AIB 1.2 spec, and that's clearly a physical interface definition to connect the FPGA core to the P-Tile chiplet. The API we need would define the P-Tile parameters and the hardware configuration method for the chiplet at the hardware-reset level ... that should happen waaay before software gets involved. Presumably we can come forward with the same system architecture as found in the factory-included example design, where Intel/Altera implements the Avalon-MM IP core as a "generic component" and just unrolls the 2000-ish parameters as a long flat list.
