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jmcguire3's avatar
jmcguire3
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Quartus P-Tile PCIe IP config crashes

Trying to configure a basic PCIe interface on the Agilex F014 EVM, and the P-Tile IP configuration crashes if I disable either the read-data-mover or write-data-mover functions under the Avalon-MM Se...
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


Is there anything else you think I can help/clarified more ?


Regards,

Wincent_Intel


jmcguire3's avatar
jmcguire3
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

That's a very bot-like reply, though it's probably a hot-key-mapped scripted response. Likely, your hand is hovering over the key to issue:

  • We have not hear from you and this Case is idling. It is not recommended to idle for too long.
  • Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause
  • Hence, This thread will be transitioned to community support.

You've verified that the problem exists, but "talk to your sales rep" isn't much "help."

If you're inclined to punt this into Community Support mode, you'll need to publish the P-Tile API so we community members can do something with it. The P-Tile lives between the FPGA fabric and the PCIe pins, so we can't bypass the P-Tile with a custom design.

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,

    Please accept my apologies for any inconvenience caused to you.
    As all the spec is mentioned in the user guide, there might have some limitation on it.
    If the MSI-X feature is important for you in the MCDMA mode, I will help to submit an internal ticket on the feature request.
    Hope the team will consider to include it in the future release version of software.

    Is there anything else you think I can assist you better ? Please let me know

    Regards,

    Wincent_Intel

    • jmcguire3's avatar
      jmcguire3
      Icon for Occasional Contributor rankOccasional Contributor
      3 years ago

      All things being equal, I'd rather that Intel/Altera would fix the bug(s) in the PCIe Avalon-MM IP core and not discontinue it. I find it difficult to believe that I'm the only engineer on the planet who wants to be able to poke memory locations and respond to peripheral interrupts via PCIe.