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jmcguire3's avatar
jmcguire3
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Quartus P-Tile PCIe IP config crashes

Trying to configure a basic PCIe interface on the Agilex F014 EVM, and the P-Tile IP configuration crashes if I disable either the read-data-mover or write-data-mover functions under the Avalon-MM Se...
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,

I dont get your question, is there any relationship between MSI-X feature and read-data-mover or write-data-mover functions under the Avalon-MM Settings tab that you mention early ?

Regards,

Wincent_Intel

  • jmcguire3's avatar
    jmcguire3
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Intel is deprecating the PCIe Avalon-MM IP core, and recommends not-using it in new designs. (Post #4, above.) In the immediately following sentence, Intel recommends that customers should use the MCDMA core instead. I explored the possibility of using it.

    My application performs reads and writes to memory-mapped ports in response to interrupts from the target device. Think "closed loop feedback machine control" and not "streaming cat videos." We currently implement interrupt support via the legacy MSI functions. Our host system is running an interrupt-driven executive.

    The MCDMA IP core does not appear to support MSI. However there is an MSI-X tab, which suggests that interrupts could be implemented via the message-based construct, albeit with a substantial increase in level-of-effort to do so. Unfortunately, MSI-X support appears to be "not functional." Intel's recommended "use the MCDMA core" is only a solution for a subset of the customer base who don't use interrupts ...