Quartus P-Tile PCIe IP config crashes

I am working with multiple platforms that have PCIe interconnect as the only available control-plane interaction. These are deployed systems, so a design constraint is to use the existing memory-mapped PCIe control paradigm. The host controller sets operating parameters via memory-mapped port writes, reads machine status via port reads, responds to interrupts on the various cards, and blinks LEDs ... you know, normal hardware-system tasks. The target cards are big state machines with no local processor.

The system does not operate with DMA-anything. We are not transferring blocks of data in a packet/protocol structure. We disabled the DMA data movers because they have zero place in our system architecture. We just need memory-mapped control ports, and legacy interrupts to trigger event responses. We have these operational with Stratix 10 and Cyclone 10 FPGAs, and they work fine. We are migrating to an Agilex-based design, and that's where we bashed into the P-Tile support issue. Functionally, the P-Tile should be able to handle a memory-mapped Avalon interface.

We found this bit in the documentation disturbing -

Note: Do not use the P-tile Avalon® Memory-mapped IP for PCI Express* for new designs. This IP will not be available in future releases of Intel® Quartus® Prime. For new designs, use the Multi-Channel DMA IP.

(ref: https://www.intel.com/content/www/us/en/docs/programmable/683853/21-1-4-0-0/design-example-overview.html )

Not sure why Intel/Altera would think that there's no place for direct-mapped port-I/O construct in a hardware-based platform ...