Occasional Contributor
Regular ContributorHi,
I wish to follow up with you about this case.
Do you have any further questions on this matter ?
Regards,
Wincent_Intel
Occasional ContributorI am working with multiple platforms that have PCIe interconnect as the only available control-plane interaction. These are deployed systems, so a design constraint is to use the existing memory-mapped PCIe control paradigm. The host controller sets operating parameters via memory-mapped port writes, reads machine status via port reads, responds to interrupts on the various cards, and blinks LEDs ... you know, normal hardware-system tasks. The target cards are big state machines with no local processor.
The system does not operate with DMA-anything. We are not transferring blocks of data in a packet/protocol structure. We disabled the DMA data movers because they have zero place in our system architecture. We just need memory-mapped control ports, and legacy interrupts to trigger event responses. We have these operational with Stratix 10 and Cyclone 10 FPGAs, and they work fine. We are migrating to an Agilex-based design, and that's where we bashed into the P-Tile support issue. Functionally, the P-Tile should be able to handle a memory-mapped Avalon interface.
We found this bit in the documentation disturbing -
Note: Do not use the P-tile Avalon® Memory-mapped IP for PCI Express* for new designs. This IP will not be available in future releases of Intel® Quartus® Prime. For new designs, use the Multi-Channel DMA IP.
Not sure why Intel/Altera would think that there's no place for direct-mapped port-I/O construct in a hardware-based platform ...
Regular ContributorHi,
I did a double-check on that, what wroten in the user is correct.
If you believe your business case justifies that Intel should invest in providing P-tile Avalon® Memory-mapped IP for PCI Express*
My suggestion will be please work directly with your cognizant Sales/FAE to submit this feature request.
Regards,
Wincent_Intel
Occasional ContributorThank you for verifying.
Not sure how we are going to proceed. Intel's recommendation to use the Multi-Channel DMA IP for memory-mapped applications doesn't appear to be a workable solution - legacy MSI interrupts aren't supported, and MSI-X interrupts appear to be broken as far back as 22.1 ... seems you're SOL if you need interrupt support across the PCIe connection.
The following summarizes known issues in the current IP release [v22.1]:
- Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1 and earlier, the User MSI-X feature in the Multi Channel DMA Intel FPGA IP for PCI Express is not functional.
https://www.intel.com/content/www/us/en/docs/programmable/683821/22-1/known-issues.html
Explains why the MSI-X radio button and subtended selections in Quartus are not-selectable.
