Quartus' own Single Port RAM template infers Dual Port RAM with pass-through logic

I think there are some features you can use by instantiating a megafunction that RAM inference intentionally does not support in Quartus integrated synthesis. Clock enable might be one of those things (possibly because of the other control signals gregsmith tried to use at the same time). For a short-term solution, a third-party synthesis tool might have more capability than Quartus integrated synthesis for RAM inference. For a future solution, you can file a service request to ask that Quartus integrated synthesis support what you want to do.

I recently had a design where I turned off "Allow Synchronous Control Signals" project wide in "More Analysis & Synthesis Settings". I needed it off on portions of the design and tried doing it on the whole project instead of doing it on individual blocks of hierarchy through the Assignment Editor. That setting prevented inference of some of the memories. If gregsmith ever changed anything in "More Analysis & Synthesis Settings", see whether that setting was turned off.