Quartus' own Single Port RAM template infers Dual Port RAM with pass-through logic

Just a short follow up. Apparently, the template in Quartus II 7.2 is wrong. The one below works as expected. Now my next question is how to infer dual port memory without bypass. I suspect you can't (without messing with synthesizer settings which is not a portable solution).

Thanks

Tommy

module single_port_ram

(

input [(DATA_WIDTH-1):0] data,

input [(ADDR_WIDTH-1):0] addr,

input we, clk,

output [(DATA_WIDTH-1):0] q

);

parameter DATA_WIDTH = 8;

parameter ADDR_WIDTH = 6;

// Declare the RAM variable

reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];

reg [ADDR_WIDTH-1:0] addr_reg;

always @ (posedge clk)

begin

// Write

if (we) ram[addr] <= data;

addr_reg <= addr;

end

// Read returns NEW data at addr if we == 1'b1. This is the

// natural behavior of TriMatrix memory blocks in Single Port

// mode

assign q = ram[addr_reg];

endmodule