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Altera_Forum
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10 years ago

Quartus not synthesizing my FSM right?

I made a FSM in verilog that is working in simulation. I found a strange behaviour however, when I synthesize it in Quartus 2. The state WRITE should immediately go to WRITE_DONE, which it does. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

the control signals are inputs to the module. They are direct outputs from a mux, but the source is coming from another block which has the same clock, so they are synchronized to the clock.

As part of my debugging, I tried replacing 'ye' if the if statement of that state to ye_reg (a registered version of the input directly in this module), but it still didn't work.

Also, when I look at the control inputs to the module in SignalTap, they are static during the time the state changes (ye_reg included).

As a test, I also tried to remove the if statement and make WRITE_DONE stay in that state if it reaches it. This did happen. I also replaced the 'ye' condition in WRITE_DONE with a small counter, so that it should wait to reach a count value before moving to next state - it didn't do that and just went right to YE_PROG2.

So somehow, when I get to this state, it seems to be ignoring the 'if' statement (whatever the condition) and just passing on to the next YE_PROG2 state.

I don't have any other idea how I can debug this.