Quartus not synthesizing logic elements

Hello all,

So I've been trying to estimate how much space a design will take on my FPGA, and it keeps on telling me it compiles/synthesizes with zero logic elements. I made sure the top level entity has inputs and outputs, and I even redid my design so it uses the switches for one of the inputs, and outputs to LED lights, but it still seems to be ripping out all my logic. I have simulated it in modelsim and it behaves as expected, with my output varying as I force the switches to different values. Any thoughts?

My Code is below, where the lower 9 switches are acting as one of my inputs, the uppermost one is acting as my "clock", controlling my flip flops basically flipping between two sets of data. I made one part controlled by the bottom most switches so the synthesizer didn't figure out the output was just varying between two values, but it still goes to 0 logic elements.

Appreciate the help

module TopModule(SW, answer, LEDG, LEDR);
    parameter granularity = 9;
    input SW;
    output answer;
    output  LEDR;
    output  LEDG;
    wire test;
    wire result;
    reg signed  Dx1;
    reg signed  Dy1;
    reg signed  Dz1;
    reg signed   Ex1;
    reg signed Ey1;
    reg signed Ez1;
    reg signed   Fx1;
    reg signed Fy1;
    reg signed Fz1;
    reg signed  Dx2;
    reg signed  Dy2;
    reg signed  Dz2;
    reg signed   Ex2;
    reg signed Ey2;
    reg signed Ez2;
    reg signed   Fx2;
    reg signed Fy2;
    //reg signed Fz2;
    initial begin
    //clk = 0;
    Dx1 = 3;
    Dy1 = 3;
    Dz1 = 1;
    Ex1 = 6;
    Ey1 = 3;
    Ez1 = 1;
    Fx1 = 4;
    Fy1 = 3;
    Dx2 = 3;
    Dy2 = 6;
    Dz2 = 1;
    Ex2 = 6;
    Ey2 = 6;
    Ez2 = 1;
    Fx2 = 4;
    Fy2 = 6;
    end
    always @ (posedge SW)
    begin
    Dx1 <= Dx2;
    Dy1 <= Dy2;
    Dz1 <= Dz2;
    Ex1 <= Ex2;
    Ey1 <= Ey2;
    Ez1 <= Ez2;
    Fx1 <= Fx2;
    Fy1 <= Fy2;
    Fz1 <= SW;
    Dx2 <= Dx1;
    Dy2 <= Dy1;
    Dz2 <= Dz1;
    Ex2 <= Ex1;
    Ey2 <= Ey1;
    Ez2 <= Ez1;
    Fx2 <= Fx1;
    Fy2 <= Fy1;
    end
    assign LEDR = 0;
    assign LEDR = answer;
    assign LEDG = 0;
    assign LEDG = ~answer;
    assign test = result;
    geometric test1(.Dx(Dx1), .Dy(Dy1), .Dz(Dz1), .Ex(Ex1), .Ey(Ey1), .Ez(Ez1), .Fx(Fx1), .Fy(Fy1), .Fz(Fz1),.output(result));
    assign answer = test;
    endmodule