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Then when I try to create the vhd file I get loads of this warning series.
Warning (275016): Found Altera-specific megafunction, primitive or component "7400"
Error (275069): Design file contains illegal characters for Verilog HDL
Error (275069): Design file contains illegal characters for Verilog HDL
Error (275069): Design file contains illegal characters for Verilog HDL
The 7400 I am using is an Altera function. Why on earth would it have illegal characters in it?
There is no information given on how to resolve this, or where to find the problem.
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7400 parts are very old.
7400 is not a legal name to give anything in VHD or Verilog, as it contains only numbers. VHDL and Verilog identifiers must start witha character.
I suggest you use parts other than the 7400 ones if you want to convert to HDL
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