Quartus Master Clock Warning - PLL output driving 2nd PLL Input

I was able to get a response via mySupport on this issue. The short is that, for cascaded plls, one cannot use derive_pll_clocks in the .sdc file. 'create_generated_clock' is necessary.

To help with this, they pointed to AN471 pg13-15 for creating the generated clock for a switchover PLL.

They also suggest the following steps to help create the 'create_generated_clock' syntax.

1. Comment out derive_pll_clock in SDC

2. In tcl console window of TimeQuest, type derive_pll_clocks

3. tcl console window will update with the correct create_generated_clock constraints

4. copy the constraints and add into SDC file.

In short, this is what I ended with:

create_generated_clock -source {PLL1|altpll_component|auto_generated|pll1|inclk[1]} -multiply_by 10 -duty_cycle 50.00 -name {PLL1|altpll_component|auto_generated|pll1|clk[0]~1} {PLL1|altpll_component|auto_generated|pll1|clk[0]}

create_generated_clock -add -source {PLL1|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 10 -duty_cycle 50.00 -name {PLL1|altpll_component|auto_generated|pll1|clk[0]} {PLL1|altpll_component|auto_generated|pll1|clk[0]}

create_generated_clock -source {PLL2|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 5 -duty_cycle 50.00 -name {PLL2|altpll_component|auto_generated|pll1|clk[0]} {PLL2|altpll_component|auto_generated|pll1|clk[0]} -master {PLL1|altpll_component|auto_generated|pll1|clk[0]}