Quartus II (v10.0) + Cyclone II : JTAG Issues

Dear all,

I have a JTAG chain of two devices. The first is a TI processor and the second a Cyclone II FPGA.

Using the TI JTAG emulator and configuring it to 'bypass' the cyclone II with an instruction register length of 10, we have never had any problems with connectivity.

Using Quartus II (v10.0) with a USB Blaster (rev C) we have never successfully been able to program. When using the Quartus II JTAG chain debugger, it successfully detects the right device when I run 'Test JTAG Chain' (See image2.jpg attached) but it does not pickup the first device. When I run the IDCODE scanner it does pick up both devices but reports back a warning (see image1.jpg). I have noticed that if I run the IDCODE scanner over and over sometimes the IDCODE reported back of the TI processor changes implying to me data integrity issues.

Alternate JTAG chain debuggers have reported back a JTAG chain length of 48 bits (Instruction register scanner), which with the cyclone II @ 10, leaves 38 for the TI DSP which seems coherent with some of their other processors (The processor I am using does not appear explicitely in any of their lists). The IDCODE scanner reports back an instruction register length of 255 for the 'Unknown' device, which I know is incorrect.

I have already taken the flat ribbon cable out of the equation by essentially eliminating it. The only thing I noticed was that the IDCODE scanner became a bit more consistent, but still always flagging the warning.

I will continue to assume this is a hardware level issue and start inserting things like series termination resistors to see what happens.

For now I raise the inquiry to see what others think/have seen.

Many thanks in advance,

James