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Altera_Forum
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15 years ago

Quartus II (v10.0) + Cyclone II : JTAG Issues

Dear all, I have a JTAG chain of two devices. The first is a TI processor and the second a Cyclone II FPGA. Using the TI JTAG emulator and configuring it to 'bypass' the cyclone II with ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

My little module board came in and I tested, with a shortened USB Blaster cable:

1. Series termination

2. A.C. parallel

3. Buffer stage

On 2 and 3 my signals were clean as distilled water and I still had the same problem.

My solution unfortunately is going to have to be the same as yours. I have to leave the JTAG RST line on my DSP pulled low to allow its TDO to float and I hit the test point tied to this to inject the USB Blaster TDI straight into the FPGA (second in chain).

How annoying. I have lost my confidence in long chains with Altera equipment inline. The TI DSP seemed to handle the whole chain just fine.